Field of the Invention
The present invention relates to a technique to verify bypass capacitor arrangement in order to suppress noise, which occurs from power source pins of the IC, within a printed circuit board by taking into account the IC package.
Description of the Related Art
As the signal speed becomes higher in an integrated circuit (IC) or in a large-scale integration (LSI), simultaneous switching noise becomes larger. In the case where the simultaneous switching noise becomes large, the power source voltage fluctuates, and therefore, a malfunction or poor signal transmission occurs in the IC or LSI, and in the case where the simultaneous switching noise is caused to propagate to the outside of the board, the radiation noise characteristics become worse. In order to avoid these problems, a bypass capacitor is arranged in the vicinity of the power source pin of the IC.
As a technique to appropriately arrange a bypass capacitor, in Japanese Patent Laid-Open No. 2002-16337, a technique has been disclosed that displays measures and instructions in the case where the length of the wiring that connects the power source pin of the IC and the power source pin of the bypass capacitor is equal to or greater than a predetermined length based on the design information on the printed circuit board.
However, with the technique disclosed in Japanese Patent Laid-Open No. 2002-16337, it is not possible to verify the bypass capacity arrangement with high accuracy because the in-package wiring of the IC is not taken into account.